Charge coupled device (CCD) image processors of the prior art are disclosed in Nudd et al, "A Charge Coupled Device Image Processor For Smart Sensor Applications," Proceedings Of The Society Of Photo-Optical Instrumentation Engineers, Vol. 155 pages 15 through 22 (Aug. 30-31, 1978, San Diego, Calif.) and Fouse et al., "Implentation Of Image Preprocessing Functions Using CCD LSI Circuits," Proceedings Of The Society Of Photo-Optical Instrumentation Engineers, Vol. 225 pages 118-130 (April 8-9, 1980, Washington, D.C.). Prior art image processors formed on a single silicon substrate with the imager and the image memory suffer from one of two alternative disadvantages, namely, an excessive amount of space is consumed on the silicon substrate, or else speed and performance are sacrificed. For example, FIG. 1 on page 16 of the above-referenced Nudd publication illustrates a parallel processing concept which maximizes the speed at which image data may be processed but suffers from the disadvantage that the processor occupies an area on the silicon substrate comparable to that occupied by the imager memory. The number of horizontal row elements in the CCD processor must be equal to the number of rows in the image memory, a significant limitation. Alternatively, space may be conserved by using a serial processor of the type illustrated in FIGS. 6 and 7 on page 20 of the above-referenced Nudd publication. However, these require that all the data in the CCD image memory be transferred one row at a time, toward the three-by-three floating gate arrays illustrated therein, thus significantly limiting the speed at which the data from the image memory may be processed. Thus, in the prior art it has not seemed possible to simultaneously achieve the high speed of parallel processing while at the same time reducing the substrate area required by the parallel processor.